From a8704aef739cdff421630c0a13121b69c816d8bd Mon Sep 17 00:00:00 2001 From: xelix Date: Wed, 29 Apr 2026 21:18:38 +0200 Subject: [PATCH 1/2] fix spi for esp change that clock_pin connects to the right signal (fspiclk instead of spiclk) fix the fifo_fill function so that the rest bytes when the length of the message is not divisible by 4 get also transmitted --- port/espressif/esp/src/hal/spi.zig | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/port/espressif/esp/src/hal/spi.zig b/port/espressif/esp/src/hal/spi.zig index d73020b9b..20c66ac2e 100644 --- a/port/espressif/esp/src/hal/spi.zig +++ b/port/espressif/esp/src/hal/spi.zig @@ -224,7 +224,7 @@ pub const SPI = enum(u2) { } if (pins.clk) |clk_pin| { - clk_pin.connect_peripheral_to_output(.{ .signal = .spiclk }); + clk_pin.connect_peripheral_to_output(.{ .signal = .fspiclk }); } } @@ -379,6 +379,11 @@ pub const SPI = enum(u2) { word = 0; } } + + //add remaining bytes + if (len % 4 != 0) { + fifo[len / 4] = word; + } } fn read_fifo(self: SPI, iter: *SliceVector([]u8).Iterator, len: usize) void { From 367b0aa6a105c171d4e6a4f056b481e4475355d5 Mon Sep 17 00:00:00 2001 From: Grazfather Date: Wed, 29 Apr 2026 22:28:12 -0400 Subject: [PATCH 2/2] Apply suggestion from @Grazfather --- port/espressif/esp/src/hal/spi.zig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/port/espressif/esp/src/hal/spi.zig b/port/espressif/esp/src/hal/spi.zig index 20c66ac2e..e62aa9f6b 100644 --- a/port/espressif/esp/src/hal/spi.zig +++ b/port/espressif/esp/src/hal/spi.zig @@ -380,7 +380,7 @@ pub const SPI = enum(u2) { } } - //add remaining bytes + // Add remaining bytes if (len % 4 != 0) { fifo[len / 4] = word; }