From c0b93d15a2be935fafc393aa309ff418cec1d9dd Mon Sep 17 00:00:00 2001 From: laidene <228526434@qq.com> Date: Thu, 2 Apr 2026 09:36:07 +0800 Subject: [PATCH] [docs][libcpu][arm][cortex-a] correct TLBIALL comments in start_gcc.S --- libcpu/arm/cortex-a/start_gcc.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 2beef86a93c..300d83df98a 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -182,7 +182,7 @@ continue_exit: /* invalidate TLB, I-cache and branch predictor */ mov r0, #0 - mcr p15, 0, r0, c8, c7, 0 /* ITLBIALL */ + mcr p15, 0, r0, c8, c7, 0 /* TLBIALL */ mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ dsb @@ -268,7 +268,7 @@ enable_mmu_page_table_early: /* invalidate TLB, I-cache and branch predictor */ mov r0, #0 - mcr p15, 0, r0, c8, c7, 0 /* ITLBIALL */ + mcr p15, 0, r0, c8, c7, 0 /* TLBIALL */ mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ @@ -660,7 +660,7 @@ rt_hw_mmu_switch: /* invalidate TLB, I-cache and branch predictor */ mov r0, #0 - mcr p15, 0, r0, c8, c7, 0 /* ITLBIALL */ + mcr p15, 0, r0, c8, c7, 0 /* TLBIALL */ mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ mcr p15, 0, r0, c7, c5, 6 /* BPIALL */