From e9b966908283aef3d7098e3180ad167506435613 Mon Sep 17 00:00:00 2001 From: Rajaganesh Rathinasabapathi Date: Thu, 9 Jul 2026 08:11:08 +0000 Subject: [PATCH] arm64: dts: aspeed: configure SCU1 uart-clk-source Add uart-clk-source to the AST2700 SCU1 syscon node. UART defaults to UXCLK (supports up to 115200 baud). For high-speed UART (>115200), UART clock source must switch to HUXCLK. The uart-clk-source bitfield controls this per UARTx (LSB-first), so set it to <0xfff> for all instances. Tested: Verified on kenya. uart-clk-source is present under syscon1:syscon@14c02000 with value <0xff0>. Signed-off-by: Rajaganesh Rathinasabapathi --- arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi index d217f1529ab5c4..daa4bf1aff6eb4 100644 --- a/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi +++ b/arch/arm64/boot/dts/aspeed/aspeed-g7.dtsi @@ -1441,6 +1441,7 @@ #size-cells = <2>; #clock-cells = <1>; #reset-cells = <1>; + uart-clk-source = <0xfff>; /* bit[x]: 0 uxclk, 1 huxclk */ scu_ic2: interrupt-controller@100 { #interrupt-cells = <1>;